/************************************************************************************* * Multi2Sim Simulator @ LaCASA Laboratory (lacasa.uah.edu) * This file shows the Multi2Sim memory system configuration parameters * for detailed simulation, including their default values. * * Authors: Aleksandar Milenkovic, Amrish K. Tewar * * Email: milenkovic@computer.org; akt0001@uah.edu * * Date: October 2014 *************************************************************************************/ <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< [milenka@eb136i-nsf02 m2s]$ m2s --mem-help ; Multi2Sim 4.2 - A Simulation Framework for CPU-GPU Heterogeneous Computing ; Please use command 'm2s --help' for a list of command-line options. ; Simulation alpha-numeric ID: xMAfR Option '--mem-config ' is used to configure the memory system. The configuration file is a plain-text file in the IniFile format. The memory system is formed of a set of cache modules, main memory modules, and interconnects. Interconnects can be defined in two different configuration files. The first way is using option '--net-config ' (use option '--help-net-config' for more information). Any network defined in the network configuration file can be referenced from the memory configuration file. These networks will be referred hereafter as external networks. The second option to define a network straight in the memory system configuration. This alternative is provided for convenience and brevity. By using sections [Network ], networks with a default topology are created which include a single switch, and one bidirectional link from the switch to every end node present in the network. The following sections and variables can be used in the memory system configuration file: Section [General] defines global parameters affecting the entire memory system. Frequency = (Default = 1000) Frequency of the memory system in MHz. PageSize = (Default = 4096) Memory page size. Virtual addresses are translated into new physical addresses in ascending order at the granularity of the page size. PeerTransfers = (Default = transfers) Whether or not transfers between peer caches are used. Section [Module ] defines a generic memory module. This section is used to declare both caches and main memory modules accessible from CPU cores or GPU compute units. Type = {Cache|MainMemory} (Required) Type of the memory module. From the simulation point of view, the difference between a cache and a main memory module is that the former contains only a subset of the data located at the memory locations it serves. Geometry = Cache geometry, defined in a separate section of type [Geometry ]. This variable is required for cache modules. LowNetwork = Network connecting the module with other lower-level modules, i.e., modules closer to main memory. This variable is mandatory for caches, and should not appear for main memory modules. Value can refer to an internal network defined in a [Network ] section, or to an external network defined in the network configuration file. LowNetworkNode = If 'LowNetwork' points to an external network, node in the network that the module is mapped to. For internal networks, this variable should be omitted. HighNetwork = Network connecting the module with other higher-level modules, i.e., modules closer to CPU cores or GPU compute units. For highest level modules accessible by CPU/GPU, this variable should be omitted. HighNetworkNode = If 'HighNetwork' points to an external network, node that the module is mapped to. LowModules = [ ...] List of lower-level modules. For a cache module, this variable is required. If there is only one lower-level module, it serves the entire address space for the current module. If there are several lower-level modules, each served a disjoint subset of the address space. This variable should be omitted for main memory modules. BlockSize = Block size in bytes. This variable is required for a main memory module. It should be omitted for a cache module (in this case, the block size is specified in the corresponding cache geometry section). Latency = Memory access latency. This variable is required for a main memory module, and should be omitted for a cache module (the access latency is specified in the corresponding cache geometry section). Ports = Number of read/write ports. This variable is only allowed for a main memory module. The number of ports for a cache is specified in a separate cache geometry section. DirectorySize Size of the directory in number of blocks. The size of a directory limits the number of different blocks that can reside in upper-level caches. If a cache requests a new block from main memory, and its directory is full, a previous block must be evicted from the directory, and all its occurrences in the memory hierarchy need to be first invalidated. This variable is only allowed for a main memory module. DirectoryAssoc = Directory associativity in number of ways. This variable is only allowed for a main memory module. AddressRange = { BOUNDS | ADDR DIV
MOD EQ } Physical address range served by the module. If not specified, the entire address space is served by the module. There are two possible formats for the value of 'Range': With the first format, the user can specify the lowest and highest byte included in the address range. The value in must be a multiple of the module block size, and the value in must be a multiple of the block size minus 1. With the second format, the address space can be split between different modules in an interleaved manner. If dividing an address by
and modulo makes it equal to , it is served by this module. The value of
must be a multiple of the block size. When a module serves only a subset of the address space, the user must make sure that the rest of the modules at the same level serve the remaining address space. Section [CacheGeometry ] defines a geometry for a cache. Caches using this geometry are instantiated [Module ] sections. Sets = (Required) Number of sets in the cache. Assoc = (Required) Cache associativity. The total number of blocks contained in the cache is given by the product Sets * Assoc. BlockSize = (Required) Size of a cache block in bytes. The total size of the cache is given by the product Sets * Assoc * BlockSize. Latency = (Required) Hit latency for a cache in number of cycles. Policy = {LRU|FIFO|Random} (Default = LRU) Block replacement policy. MSHR = (Default = 16) Miss status holding register (MSHR) size in number of entries. This value determines the maximum number of accesses that can be in flight for the cache, including the time since the access request is received, until a potential miss is resolved. Ports = (Default = 2) Number of ports. The number of ports in a cache limits the number of concurrent hits. If an access is a miss, it remains in the MSHR while it is resolved, but releases the cache port. DirectoryLatency = (Default = 1) Latency for a directory access in number of cycles. EnablePrefetcher = {t|f} (Default = False) Whether the hardware should automatically perform prefetching. The prefetcher related options below will be ignored if this is not true. PrefetcherType = {GHB_PC_CS|GHB_PC_DC} (Default GHB_PC_CS) Specify the type of global history buffer based prefetcher to use. GHB_PC_CS - Program Counter indexed, Constant Stride. GHB_PC_DC - Program Counter indexed, Delta Correlation. PrefetcherGHBSize = (Default = 256) The hardware prefetcher does global history buffer based prefetching. This option specifies the size of the global history buffer. PrefetcherITSize = (Default = 64) The hardware prefetcher does global history buffer based prefetching. This option specifies the size of the index table used. PrefetcherLookupDepth = (Default = 2) This option specifies the history (pattern) depth upto which the prefetcher looks at the history to decide when to prefetch. Section [Network ] defines an internal default interconnect, formed of a single switch connecting all modules pointing to the network. For every module in the network, a bidirectional link is created automatically between the module and the switch, together with the suitable input/output buffers in the switch and the module. DefaultInputBufferSize = Size of input buffers for end nodes (memory modules) and switch. DefaultOutputBufferSize = Size of output buffers for end nodes and switch. DefaultBandwidth = Bandwidth for links and switch crossbar in number of bytes per cycle. Section [Entry ] creates an entry into the memory system. An entry is a connection between a CPU core/thread or a GPU compute unit with a module in the memory system. Arch = { x86 | Evergreen | SouthernIslands | ... } CPU or GPU architecture affected by this entry. Core = CPU core identifier. This is a value between 0 and the number of cores minus 1, as defined in the CPU configuration file. This variable should be omitted for GPU entries. Thread = CPU thread identifier. Value between 0 and the number of threads per core minus 1. Omitted for GPU entries. ComputeUnit = GPU compute unit identifier. Value between 0 and the number of compute units minus 1, as defined in the GPU configuration file. This variable should be omitted for CPU entries. DataModule = ConstantDataModule = InstModule = In architectures supporting separate data/instruction caches, modules used to access memory for each particular purpose. Module = Module used to access the memory hierarchy. For architectures supporting separate data/instruction caches, this variable can be used instead of 'DataModule', 'InstModule', and 'ConstantDataModule' to indicate that data and instruction caches are unified. >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>